Working for a fascinating semiconductor company focused on RISC-V core IP development, your responsibilities will include, but are not limited to:
1. Deliver RTL to the SoC team.
2. Support verification and silicon validation teams.
3. Work with SW teams to support successful deployments of the system.
4. Evaluate new IPs and drive new IP deployments.
5. Define system-wide guidelines for IP requirements in the SoC.
6. Closely drive resolution of issues and bugs that are gating the completion of the schedule.
Skills:
1. 5+ years of solid experience in IP/SoC design.
2. Good understanding of ASIC design, verification, and implementation flows.
3. Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure, and verification.
4. Hands-on experience with SoC Design, Verilog RTL coding, and simulation software.
5. General knowledge of synthesis, DFT, verification, formal verification, and silicon debug.
6. Working knowledge with SystemVerilog or Verilog, C or C++, and scripting languages such as Python.
MUST HAVE: Excellent communication skills (ideally in English, Spanish, or Catalan).
Visa sponsorship and relocation support are available for highly skilled and relevant qualified engineers.
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